Level 1 SPICE models for NMOS and PMOS devices of “Design of Analog CMOS Integrated Circuits”

The well known book Design of Analog cmos Integrated Circuits by renowned Professor Behzad Razavi always rely on the table 2.1 for many of the practice questions as well as in its other chapters, it would be easier to put that into a webpage for reference rather than flipping through pages to find the table.

On the 2nd edition of the book, this table resides in page 35 of Section 2.4. This part describes the level 1 MOS SPICE model corresponding to 0.5 micrometer technology. Section 17.3 also introduces other models for more advanced description of new technologies, which will also be mentioned in this article.

For Triode Region

I_{D}=\frac{1}{2}K_{P}\frac{W}{L-2L_{D}}\left[2\left(V_{GS}-V_{TH}\right)V_{DS}-V_{DS}^{2}\right]\left(1+\lambda V_{DS}\right)

For Saturation Region

I_{D}=\frac{1}{2}K_{P}\frac{W}{L-2L_{D}}\left(V_{GS}-V_{TH}\right)^{2}\left(1+\lambda V_{DS}\right)
namenmos valuepmos valueunitexplanation
LEVEL11model level
VTO0.7-0.8Vthreshold voltage
GAMMA0.450.4V^{\frac{1}{2}}body-effect coefficient
PHI0.90.8V2\Phi_{F}
NSUB9e+149e-9cm^{-3}substrate doping
LD0.08e-60.09e-6msource/drain side diffusion
UO350100cm^{2}/V/schannel mobility
LAMBDA0.10.2V^{-1}channel-length modulation coefficient
TOX9e-99e-9mgate-oxide thickness
PB0.90.9Vsource/drain junction built-in potential
CJ0.56e-30.94e-3F/m^{2}source/drain bottom-plate junction capacitance per unit area
CJSW0.35e-110.35e-11F/msource/drain sidewall junction capacitance per unit length
MJ0.450.5exponent in CJ euqations
MJSW0.20.3exponent in CJSW equations
CGDO0.4e-90.3e-9F/mgate-drain overlap capacitance per unit width
CGSOF/mgate-source overlap capacitance per unit width
JS1.0e-80.5e-8A/m^{2}source/drain leakage current per unit area
Level 1 SPICE models for NMOS and PMOS devices

A table with only values is also provided for copying purpose:

namenmos valuepmos value
LEVEL11
VTO0.7-0.8
GAMMA0.450.4
PHI0.90.8
NSUB9e+149e-9
LD0.08e-60.09e-6
UO350100
LAMBDA0.10.2
TOX9e-99e-9
PB0.90.9
CJ0.56e-30.94e-3
CJSW0.35e-110.35e-11
MJ0.450.5
MJSW0.20.3
CGDO0.4e-90.3e-9
CGSO
JS1.0e-80.5e-8
Level 1 SPICE models for NMOS and PMOS devices with only values.

In spice code, the above table could be transferred as follows for nmos and pmos.

.model mynmos nmos (level=1 vto=0.7 gamma=0.45 phi=0.9 nsub=9e+14 ld=0.08e-6 uo=350 lambda=0.1 tox=9e-9
+ pb=0.9 cj=0.56e-3 cjsw=0.35e-11 mj=0.45 mjsw=0.2 cgdo=0.4e-9 js=1.0e-8)
.model mypmos pmos (level=1 vto=-0.8 gamma=0.4 phi=0.8 nsub=9e-9 ld=0.09e-6 uo=100 lambda=0.2 tox=9e-9
+ pb=0.9 cj=0.94e-3 cjsw=0.35e-11 mj=0.5 mjsw=0.3 cgdo=0.3e-9 js=0.5e-8)

Conclusion

This article contains the information on L1 Spice cmos model parameters for reference.


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