ECE5505 Digital Test and Verification Notes Part I

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graph LR
    A[Start] --> A1[Annotate Stems]
    A1 --> B[Initialize fault lists for primary inputs]
    B --> C[Get next gate in topological order]
    C --> D[Compute gate output value]
    D --> E[Include gate's own stuck-at faults]
    E --> F[Propagate faults from inputs to gate output]
    F --> G[Update fault list for gate's output]
    G --> H{More gates to process?}
    H -- Yes --> C
    H -- No --> I[Collect faults at primary outputs]
    I --> J[End]

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flowchart LR
    A[#5] --> B[Fault Equivalence]
    B --> B1[Properties]
    B1--> B2[def: faults produce same output]
    B1--> B3[transitivity: f1->f2->f3, trivial]
    G --> C[Equivalent Faults Have Same Detection Vectors]
    B --> D[Equivalence Collapsing Reduces Faults]
    D --> E[from 2n to n+2 Faults]

    B --> F[⚠️Faults on Fanout Stems/Branches]
    F --> B3
    J --> F
    B --> G[Relating Faults to Test Vectors]
    G --> H[Tα = Tβ for Equivalent Faults<br>reverse wrong🛑]

    A --> J[Fault Dominance]
    J --> K[Fault α Dominates β if α ≡ β for All Vectors in Tβ]
    K --> L[If β is Detected, α is Definitely Detected]

    B --> N[If Two Faults Dominate Each Other, They are Equivalent]
    N --> O[Use Dominance to Collapse Faults]
    J --> N
    
    A-->P0
    P0[Theorem]
    R-->P[1️⃣: Fanout-Free Combinational Circuit]
    P --> Q[Test Set Detecting PI Faults Also Detects All Faults]

    P0 --> R[2️⃣: General Combinational Circuit]
    R --> S[Test Set Detecting Checkpoint Faults Detects All Faults]

    P0 --> T[3️⃣: Irredundant Circuit]
    T --> U[Test Set Detecting Single Faults Also Detects Multiple Faults]

    A --> V[Fault Classification]
    V --> W[1️⃣Untestable Fault<br>2️⃣Potentially Detectable Fault<br>3️⃣Initialization Fault<br>4️⃣X-Fault on Fanout<br>5️⃣Hyperactive Fault]

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flowchart LR
    A[#6] --> B[Fault Simulation Overview]
    B --> C[Determine Fault Coverage for Test Set]
    C --> D[Fault List that's Collapsed]
    D --> E[Fault is Removed Once Detected]
    E --> E1[defect level<br>reject rate]

    B --> F[Uses of Fault Simulation]
    F --> G[1️⃣Determine Quality of Test Set]
    G --> H[2️⃣Drop Incidentally Detected Faults in ATPG]
    H --> I[3️⃣Help Narrow Down Candidate Fault Sites in Diagnosis]

    A --> J[Techniques for Fault Simulation]
    J --> K[Serial Fault Simulation]
    J --> L[Parallel-Fault Simulation]
    J --> M[Parallel-Pattern Simulation]
    J --> N[Deductive Fault Simulation]
    J --> O[Concurrent Fault Simulation]
    J --> P[Statistical Simulation]
    J --> Q[Differential Fault Simulation]

    K --> R[Serial Fault Simulation Process]
    R --> S[Inject Fault and Schedule Event]
    S --> T[Simulate and Propagate Event to Primary Output]
    T --> U[Check for Fault Detection at Primary Output]

    L --> V[Parallel-Fault Simulation Process]
    V --> W[Simulate Multiple Faults Simultaneously]
    W --> X[Check Bit Positions for Fault Detection]

    M --> Y[Parallel-Pattern Simulation Process]
    Y --> Z[Simulate Multiple Vectors Simultaneously]
    Z --> AA[Check Bit Positions for Fault Detection]

    N --> AC[Propagate Fault Sets Across Combinational Circuit]
    AC --> AD[Apply Propagation Rules]

    Q --> AF[Simulate Differences Between Consecutive Faults]
    AF --> AG[Force Values Instead of Injecting/Removing Faults]
    
    O --> O1[Create List of Replica Nodes for Each Fault at Every Gate]
    O1--> O2[deductive fault sim with a list]

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flowchart LR
    A[#7] --> B
    B[PROOFS<br>Parallel Fault Sim]--> D[Inject Fault by Inserting Extra Gate]
    D --> E[If Fault Not Excited<br>Excited&Blocked<br>Do Not Inject]

    A --> G[Fault Simulation in Sequential Circuits]
    G --> H[Store Fault Effects at Flip-Flops]
    H --> I[Insert Fault Effects from Previous Time Frame]

    A --> J[Speeding Up Fault Simulation]
    J --> K[Reduce Number of Events]
    K --> L[Fault Grouping]

    L --> M[Static Fault Grouping]
    M --> N[Random, Depth-First, Breadth-First Reordering]
    N --> N1[DF: no events under<br>BF: no events on left]
    L --> O[Dynamic Fault Grouping]
    O --> P[Groups: Inactive<br>Excitable<br>Normal<br>Hyperactive]
    P --> P1[Hyperactive: propapates to many gates but not detected]
    P--> P2[Reorder by put hyperactive together]

    J --> Q[Eliminate Potential Fault Effects<br>1/x, 0/x]
    Q1[inability to init]-->Q
    Q --> R[Faultsim from Every Starting State]
    R --> R1[truly detect]
    R --> S1
    S1[uninitable states] --> S[Statistical Sampling of Initial States]
    S --> S2[detection probability]

    J --> T[Determine Fault Coverage with Logic Simulation]
    T --> U[Critical Path Tracing]
    U --> U1[1️⃣Logic Sim<br>2️⃣Mark Sensitive<br>3️⃣trace back]
    U --> U2[stem]
    T --> V[Star Algorithm for Fault Detection]
    V -->U2
    V -->V1[1️⃣Logic Sim<br>2️⃣Mark *<br>3️⃣trace back&arcoss fanout]

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flowchart LR
    A[#8] --> B[Fault Grading / Coverage Estimation]
    B --> C[Motivation: Quick Coverage Estimate]
    
    B --> D[Fault Sampling]
    D --> E[Sample a Subset of Faultlist F]
    E --> F[Run Fault Simulation on Sample]
    F --> G[Fault Coverage Estimation Based on Sample]
    D --> G1[sample size]
    G1 -->G2[✅fc<br>🛑size of faultlist]

    B --> H[Vector Sampling]
    H --> I[Sample Test Set T]
    I --> J[Works for Combinational Circuits]

    A --> K[STAFAN<br>✴️Logic Sim only<br>fanout free]
    K --> M[Signal=1 Prob based on test set]
    M --> M3[Controllability<br>Observability]
    M3--> M4[⚠️3 AND<br>3 OR<br>NOT<br>fanout]
    M4 --> M5[⚠️Fault Detectability]
    M --> M1[Prob a F not detected by n Vs]
    M1--> M2[Prob a F is deted by at least 1 of n Vs]
    M2 --> N[Exptation Nums of Faults Detected]

    A --> O[Non-Statistical Fault Coverage Estimation]
    O --> P[Motivation: Handle Hyperactive Faults in Sequential Circuits]
    P --> Q[Categorize Faults Based on Activity and Detection Sequence]
    Q --> Q1[WANT]
    Q1-->Q2[elim hyperactive Fs early<br>elim active but undect faults early]
    
    O --> R[Hyperactive Fault Handling]
    R --> S[Declare Faults Undetected After k Time Frames]
    R --> T[Suppress Potential Effects of Hyperactive Faults]
    T --> T1[make X=fault free val]
    R --> T2[Over-specify potential effects]
    T2--> T3[x=opposite of fault free val]

    O --> U[Avoiding Active But Unpropagated Faults]
    U --> V[Order Faults in Breadth-First Manner]
    V --> W[Mark Unpropagated Faults as Unpropagatable]

    A --> X[Defect Coverage]
    X --> Y[Fault Coverage Only Measures Specific Fault Models stuckat]
    Y --> Z[Increase Defect Coverage by Testing Multiple Fault Models]
    Y --> AA[Detect Same Fault Multiple Times for Higher Observability]

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flowchart LR
    A[#13] --> B[Testing Acyclic Sequential Circuits]
    B --> C[Transform to Balanced Combinational Circuit]
    C --> D[Apply Combinational ATPG]
    D --> E[Transform Test Vectors to Test Sequence]

    A --> F[Balanced Model]
    F --> G[Internal Balancing Between Nodes]
    G --> H[Strongly Balanced: All Paths to PIs Have Same Depth]
    
    F --> I[Balanced Model Generation]
    I --> J[Compute PO Weight: Maximum Sequential Depth]
    J --> K[Duplicate/Split Gates as Needed]

    A --> L[Simulation-Based Sequential ATPG]
    L --> M[Avoid Backtracing/Backtracking]
    M --> N[Use Random Test Generation]

    A --> O[CONTEST Algorithm]
    O --> P[Phase 1: Fault-Free Initialization]
    P --> Q[Phase 2: Concurrent Fault Detection]
    Q --> R[Phase 3: Single Fault Targeting]
    
    A --> S[GA-Test]
    S --> T[Use Genetic Algorithm to Optimize Test Vectors]
    T --> U[No Single Target Fault Phase]
    
    A --> V[DIGATE Algorithm]
    V --> W[Distinguishing Sequence Learning]
    W --> X[Application to ATPG: Distinguish Faulty vs Fault-Free Machines]

    A --> Y[State Relaxation & Justification]
    Y --> Z[Use Set/Reset Sequences to Guide GA]
    
    A --> AA[Pseudo-Register Justification]
    AA --> AB[Set Groups of FFs to Specific Values]

    A --> AC[STRATEGATE: State Traversal Based]
    AC --> AD[Use Similar Previously Visited States to Justify Target States]

    A --> AE[Logic-Simulation Based Sequential ATPG]
    AE --> AF[Traverse Circuit States to Detect More Faults]
    AF --> AG[Need to Differentiate New States]