This blog serves as the 2nd and last part for the class ECE5505 Digital Test and Verification.
D Flip Flop
Delay/Data flip flop: The flip flop remains in its current state until its receives a signal like clock that switches it to opposite state. The clock single required for the synchronous version of D flip flops but not for the asynchronous one.
| Clock | Q(n) | D(n) | Q(n+1) | state |
| \uparrow\, \gg 0 | 0 | 0 | 0 | hold |
| 0 | 1 | 1 | reset | |
| 1 | 0 | 0 | reset | |
| 1 | 1 | 1 | hold |
| \overline{PR} | \overline{CLR} | CLK | D | Q | \overline{Q} |
| 0 | 1 | X | X | 1 | 0 |
| 1 | 0 | X | X | 0 | 1 |
| 0 | 0 | X | X | X | X |
| 1 | 1 | \uparrow | 1 | 1 | 0 |
| 1 | 1 | \uparrow | 0 | 0 | 1 |
| 1 | 1 | 0 | X |
Iterative Logic array
| Step | Time Frame | Procedure | optimization |
| 1 | 0 | 1️⃣ PI=PI+FF 2️⃣ PO=PO+FF 3️⃣ PODEM for PIs | reduce flip flop state vars |
| 2 | \geqslant 1 | 1️⃣Propagate to actual PO 2️⃣ frame by frame 3️⃣ TG for frames \geqslant 1backwards 🛑states could be unjustifiable, find alternative 4️⃣Additional constraints on TF0 | reduce propagate frame nums delete illegal/unreachable states |
| 3 | -1 | ✴️input seq with FF states (x) to justify TF0 1️⃣ justify FF states at time frame 0 🛑states could be unjustifiable, find alternative |
Sequential circuit with Drivability in addition to observability, controllability, drivability means drive to D or -D from g with respect to controllability.
S-Graph: vertices are FFs, edges, if acylic(not going back to itself), faulty state is always initializable, d_{seq}, num of FFs on the longest path in s-graph, non-FF fault in acyclic circuit has at most d_{seq}+1 vectors.
D algorithm – Combinational ATPG in DFT (VLSI)
extened backward implication
Extended Backward Implication1
forward implication: if all input values are known or one is controlling value, the output can be determined.
backward implication: calculate input implication by the output value.
if output=1, implicates all gate inputs are 1, add implications of setting these inputs to 1.
if ouput=0, implicates at least one of the input is 0, need to add implications of setting each of these inputs to 0 and then union to make sure at least one of inputs is 0. It is trying to constrain the implication than to conclude in case where implication to one input is 0 and implication to another input is 1. Perhaps this is because implication of only input to 0 cannot guarantee the output to be 0. Implications needs to be propagated through gates like deductive fault simulation.
\begin{aligned}
\underbrace{\text{FIRE}}_{\substack{\text{Fault Independent}\\ \text{REdundency Identification}}}&=
\underbrace{\{\text{S}_{a=0}\} \cap \{\text{S}_{a=1}\}}_{\substack{\color{blue}{\text{Faults that are untestable}}}} & \\[4ex]
&=\{\underbrace{\overline{\text{EXCT}_{a=0}}}_{\substack{\text{unexcitable faults}\\\text{when } a=0}}\cup\underbrace{\overline{\text{PROP}_{a=0}}}_{\substack{\text{unpropagatable faults}\\\text{when } a=0}}\}\cap
\{\underbrace{\overline{\text{EXCT}_{a=1}}}_{\substack{\text{unexcitable faults}\\\text{when } a=1}}\cup\underbrace{\overline{\text{PROP}_{a=1}}}_{\substack{\text{unpropagatable faults}\\\text{when } a=1}}\}
\end{aligned}Delay Path Fault
| Gate Type | Fault Type | Non-Robust | Robust |
| AND | \uparrow | \color{gray}{01}\cdot \color{red}{x1}: \color{blue}{01}/\color{brown}{00} | \color{gray}{01}\cdot \color{red}{x1}: \color{blue}{01}/\color{brown}{00} |
| AND | \downarrow | \color{gray}{10}\cdot\color{red}{x1}: \color{blue}{x0}/\color{brown}{x1} | \color{gray}{10}\cdot\color{red}{11}: \color{blue}{10}/\color{brown}{11} |
| OR | \uparrow | \color{gray}{01}+\color{red}{x0}:\color{blue}{x1}/\color{brown}{x0} | \color{gray}{01}+\color{red}{00}:\color{blue}{01}/\color{brown}{00} |
| OR | \downarrow | \color{gray}{10}+\color{red}{x0}:\color{blue}{10}/\color{brown}{11} | \color{gray}{10}+\color{red}{x0}:\color{blue}{10}/\color{brown}{11} |
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