ECE5505 Digital Test and Verification Final Project

overleaf project folder

0️⃣1️⃣A survey of digital circuit testing in the light of machine learning. ¹

0️⃣2️⃣A Survey and Recent Advances: Machine Intelligence in Electronic Testing. ²

0️⃣3️⃣✅Machine intelligence for efficient test pattern generation.³

Backtracing: identifies PIs to assign to meet ATPG objectives (e.g., exciting or propagating faults).

Backtracking: Backtracking is a class of algorithms for finding solutions to some computational problems, notably constraint satisfaction problems, that incrementally builds candidates to the solutions, and abandons a candidate (“backtracks”) as soon as it determines that the candidate cannot possibly be completed to a valid solution.

Uses Artificial Neural Network namely fully connected layer to guide through the backtracing to reduce the backtracking probability, thus it could reduce the ATPG generation time.

ANN with input of gate tyes as onehot, gate/circuit level, controllability, observability, output of sucessful backtracing probability.

For training, use the random tracing heurisitc,

0️⃣4️⃣Principal component analysis in machine intelligence-based test generation.⁴

0️⃣5️⃣✅Multi-heuristic machine intel- ligence guidance in automatic test pattern generation.⁵

0️⃣6️⃣✅Efficient and effective neural networks for automatic test pattern generation.⁶

0️⃣7️⃣❓Neural fault analysis for sat-based atpg.⁷

0️⃣8️⃣Fpgnn-atpg: An efficient fault parallel automatic test pattern generator.⁸

0️⃣9️⃣High-speed, low-storage power and thermal predictions for atpg test patterns.⁹

1️⃣0️⃣Automatic test configuration and pattern generation (atcpg) for neuromorphic chips.¹⁰

1️⃣1️⃣Deep learning based test compression analyzer.¹¹

¹²

1. Pradhan, Manjari, and Bhargab B. Bhattacharya. “A survey of digital circuit testing in the light of machine learning.” Wiley Interdisciplinary Reviews: Data Mining and Knowledge Discovery 11, no. 1 (2021): e1360.📁[↩]
2. Roy, Soham, Spencer K. Millican, and Vishwani D. Agrawal. “A Survey and Recent Advances: Machine Intelligence in Electronic Testing.” Journal of Electronic Testing (2024): 1-20.📁[↩]
3. Roy, Soham, Spencer K. Millican, and Vishwani D. Agrawal. “Machine intelligence for efficient test pattern generation.” In 2020 IEEE International Test Conference (ITC), pp. 1-5. IEEE, 2020.📁[↩]
4. Roy, Soham, Spencer K. Millican, and Vishwani D. Agrawal. “Principal component analysis in machine intelligence-based test generation.” In 2021 IEEE Microelectronics Design & Test Symposium (MDTS), pp. 1-6. IEEE, 2021.📁[↩]
5. Roy, Soham, Spencer K. Millican, and Vishwani D. Agrawal. “Multi-heuristic machine intelligence guidance in automatic test pattern generation.” In 2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS), pp. 1-6. IEEE, 2022.📁[↩]
6. Zhang, Lizi, and Azadeh Davoodi. “Efficient and Effective Neural Networks for Automatic Test Pattern Generation.” In Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, pp. 1-7. 2024.📁[↩]
7. Huang, Junhua, Hui-Ling Zhen, Naixing Wang, Hui Mao, Mingxuan Yuan, and Yu Huang. “Neural fault analysis for sat-based atpg.” In 2022 IEEE International Test Conference (ITC), pp. 36-45. IEEE, 2022.📁[↩]
8. Ye, Yuyang, Zonghui Wang, Zun Xue, Ziqi Wang, Yifei Gao, and Hao Yan. “FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator.” In Proceedings of the Great Lakes Symposium on VLSI 2023, pp. 299-304. 2023.📁[↩]
9. Liang, Zhe-Jia, Yu-Tsung Wu, Yun-Feng Yang, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, and Ying-Shiun Li. “High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns.” In 2023 IEEE International Test Conference (ITC), pp. 206-215. IEEE, 2023.📁[↩]
10. Chiu, I-Wei, Xin-Ping Chen, Jennifer Shueh-Inn Hu, and James Chien-Mo Li. “Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic Chips.” In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, pp. 1-7. 2022.📁[↩]
11. Wu, Cheng-Hung, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar Reddy, Chun-Cheng Hu, and Chong-Siao Ye. “Deep learning based test compression analyzer.” In 2019 IEEE 28th Asian Test Symposium (ATS), pp. 1-15. IEEE, 2019.📁[↩]
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