Category: Chiplets
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Cadence Training Learning Maps
This post serves as a portal for naviating through the Cadence Online Learning Courses. As there are lots of components in their product suite, the learn maps cover different aspects for IC design. The Learning Maps file is publicly available from Cadence Website, the specific course materials need access from Cadence. Cadence Training Learning Maps…
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Exploiting 2.5D/3D Heterogeneous Integration for AI Computing
References Exploiting 2.5D/3D Heterogeneous Integration for AI Computing1 Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling2 End-to-End Benchmarking of Chiplet-Based In-Memory Computing3 Summary HISIM4, a modeling and benchmarking tool for heterogeneous integration of chiplets by communicating through NoP5. Components: partitioning, mapping and placement; computing unit/processing unit; heterogeneous interconnection; network/routing engine; thermal analysis. technology roadmap6, power/latency prediction,…