Mustang Wang

Category: Integrated Circuit

  • Connected to Jim Keller

    In a surprising and truly exciting development, Jim Keller, the legendary “Silicon Sage” whose innovations have profoundly shaped the tech world, accepted my LinkedIn invitation this morning. What makes this particularly remarkable is that we’ve never actually met in person or professionally intersected in any way. It’s a testament to the open and interconnected nature of…

  • Virtuoso Annotation

    This post discusses briefly about annotation on schematics when simulation has been performed, it is not going to be a detailed summary but to get you started on annotation and ballons. Before going further, please make sure you know how to do a simulation prior to annotation configuration. In ADE Explorere’s schematic view, go to…

  • Cadence Training Learning Maps

    This post serves as a portal for naviating through the Cadence Online Learning Courses. As there are lots of components in their product suite, the learn maps cover different aspects for IC design. The Learning Maps file is publicly available from Cadence Website, the specific course materials need access from Cadence. Cadence Training Learning Maps…

  • ECE5505 Digital Test and Verification Final Project

    This blog post serves as a protal for supplementary materials for the final project report of the course ECE5505 Digital Test and Verification 24 Fall. Links are available to be redirected to the specific academic article in PDF format, it should be noted that readers should access those documents within an institution where subscriptions access…

  • ECE5505 Digital Test and Verification Notes Part I

    Introduction This is the blog for VT ECE5505 digital system test and verification course summary, it is currently working as a draft and not finalized. Simulations Fault Simulation Logic Sim Definition given a circuit, fault model, a test set, determine fault coverage determine test set qualityATPG, a vector 1️⃣Serial2️⃣Parallel-fault3️⃣Parallel-pattern4️⃣Deductive Fault Simulation5️⃣Concurrent6️⃣Critical Path Tracing7️⃣Statistical8️⃣Differential9️⃣Combined STAFAN Non-statistical…

  • HotSpot Thermal Model Notes

    Introduction Hotspot has been released to its 7 iteration with multiple updates regarding accurate thermal simulation benchmark. Installation To increase the simulation speed, the SUPERLU package is needed, depending on the various distros with own specifiic package managers, the installation could be different. Once it is installed, hotspot could be compiled. SuperLU I prefer to…

  • Setup 22nm PDK @VT

    This article is based on Professor Jeffrey Walling‘s youtube video on how to setup the 22nm PDK in Cadence Virtuoso. In addition, I will discuss a bit about X Window manager for running window apps via SSH. This article provides a specific case for setting up PDK with customized scripts, which may not be general…

  • Troubleshooting the “ERROR (OSSHNL-116)” in Cadence Virtuoso

    Introduction:In the pursuit of mastering Cadence Virtuoso, I recently encountered a perplexing error message: “ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, ‘hspiceD spice cmos_sch cmos.sch schematic’, for the instance ‘X’ in cell ‘Y’. Either add one of these views to the library ‘NCSU_Analog_Parts’, cell ‘res’ or modify…