Tag: physical-design
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Train a Transformer on Silicon: #3 The Memory Is the Chip
v0’s die was 85% SRAM. H01 packs the flat memory map with liveness analysis and an early-SGD reschedule — 145,952 words down to 90,896, the die from 6.99 to 4.55 mm², 35% smaller — without changing one logic gate. The compute was never the problem; the memory was.
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Publication-Quality Chip Layout Figures from Innovus, Headlessly
Innovus has no vector export and its GUI screenshots don’t scale. Here’s a fully scripted pipeline: a headless 16,000-pixel render, block coordinates pulled from the P&R database, a zero-residual pixel-to-micron calibration, and a matplotlib wrapper that turns it all into a self-describing PDF/SVG figure.