“Fundamentals of device and systems packaging: technologies and applications” Textbook Note

Fundamentals of device and systems packaging: technologies and applications.¹

There are many hyperlinks that redirect to the original images in the McGraw Hill site for reference.

packaging hierarchy	name	purpose	interconnection
Level 1	IC carrier Packaged-IC		IO pads on IC connected to 1st level of packaging wirebonding IC assembly
Level 2			solder bonding substrate of 1st level package and electrically conductive pads on 2nd-level package. Board assembly

Packaging Tech: Electrical(signal propagation: signal distortion, signal degradation->line resistance; power distribution: switching noise from switching all driving transistors, voltage drop, delta-I noise when switching off lots of transistors, cross talk, , Electromagnetic radiation.), Materials, Mechanical(stresses are developed due to the combined effect of mismatch in thermal expansion coefficients between various interfaces and temperature cycles.)

Category	Reason	Electrical	Material	Mechanical
propagation		signal distortion
propagation		signal degradation
propagation		speed	lowest dielectric constant dielectrics. higher-resistance lines carry less current, which slows device speed.
power		switching noise
power		voltage drop	highest electrical conductivity
power		delta-I noise	low inductance, high capacitance
power		cross talk	Higher capacitance slows electrons and can create unwanted “cross-talk”
power		EMR
			highest thermal conductivity	mismatch in thermal expansion coefficients between interfaces and temperature cycles.

Electrical, Thermal, Optimal, Substrate/Passive component/Interconnection/Assembly/Encapuslation materials and processes, Electrical test and repiar, Metrology and package characterization.

Interconnections and assembly evolution from wire bonding to flip-chip to all-copper.

There are two reasons for the eventual in validity of Moore’s Law—leakage due to tunneling current at higher electric fields and lower performance.

local interconnect, global interconnect.

On-chip interconnection wiring fabrication

copper via: typically a tantalum nitride barrier to prevent metal diffusion into the dielectric, a tantalum liner to improve barrier adherence to the metal, a copper seed layer to seed the metal plating, and finally, the core conducting bulk copper metal.

One strategy is to make the high-resistance barrier and liner thinner, difficult to make layer thinner. “self-forming” barrier that reacts with and forms on the dielectric surface adjacent to the copper line, which allows more room for copper. new liners made of cobalt and ruthenium are being developed to replace tantalum. new technologies are in place to achieve void-free copper fill of small trenches.

microelectronics, RF/wireless, photonics, and MEMS. A fifth wave, Quantum computing.

Packaging for testing and inetegrating with other ICs.

Embedded ICs trend(reduce thickness, no assembly, no substrate, shorter interconnection length)

(a) Traditional packaging, and (b) concept of embedding.

Materials: (conductor, dielectric, solder, underfill, thermal interface materials/heat speaders)

Materials in packaging.

Passive	Inteconnects	Substrate	Thermal
C L R	Solders Conductive Adhesives Nanointerconnects Underfills	Core Dielectric Conductors	Heat Spreader Thermal Interface Material

A Variety of Materials Used in Systems Packaging

An example of future systems with system-on-package (SOP) concept.

Electrical package design is a process that defines the electrical signal and power paths from the chip, through the package, to the system board to meet the overall system requirements.

	chipset	substrate	package
connect to substrate	wire bonding flip chip		ball grid array

Electrical anatomy of a package.

Power Dilivery Network: minimize parasitic inductance

At high frequencies, interconnects are physically longer than the packets of energy routed along them, and their behavior depends on the properties of the materials and the electromagnetic fields that comprise the signal.

Electrical design flow of a package for signal and power integrity.

1. Tummala, Rao R. Fundamentals of device and systems packaging: technologies and applications. McGraw-Hill Education, 2019. 📁[↩]