Tag: on-chip-training
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Train a Transformer on Silicon: #3 The Memory Is the Chip
v0’s die was 85% SRAM. H01 packs the flat memory map with liveness analysis and an early-SGD reschedule — 145,952 words down to 90,896, the die from 6.99 to 4.55 mm², 35% smaller — without changing one logic gate. The compute was never the problem; the memory was.
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Train a Transformer on Silicon: #2 A Decoder Is Just an Encoder with a Mask
v0 is done: a nanoGPT-faithful decoder layer that trains itself — forward, backprop, and SGD update — bit-exact against a golden model and taken to a clean 45 nm layout. The compute fit in 0.117 mm² of logic; the memory took 85% of the die.
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Train a Transformer on Silicon: #1 Backprop on a Chip
Most AI chips run a model someone else trained; this one does the training itself — forward pass, backpropagation, and weight update, in fixed-point RTL, all the way down to a 45 nm layout.